Circuits can be tested by means of functional tests and structural tests. Functional testing involves a determination whether the circuit properly performs the function for which it is designed. Structural testing involves performing measurements from which it can be inferred in-circuit whether the performance of all components of the circuit (including connections) is normal. An advantage of structural testing is that the same, simple, standardized measurements can be used for different types of circuit during structural testing. If the circuit has been properly designed and a structural test shows that all relevant components have normal performance, it may be expected that the circuit properly performs its function. Therefore a circuit that passes a structural test generally will also pass functional tests.
Structural testing is well established for digital circuits, but structural testing of analog circuits is less usual. One reason for this is that it is difficult to select measurements that can be applied to a circuit to detect the presence of faulty components in that circuit. In analog circuits faulty components can be components with abnormal parameter values, such as transistors with abnormal threshold voltages or current amplification factor. The effect of a faulty parameter value of a component can be more easily masked by the natural spread of the parameter values of other components in the circuit. This makes it more difficult to determine which test measurements can be used to discover the presence of faults in any, or most components. For digital circuits planning of test measurements involves selecting a set of possible structural faults and determining test measurements that can be applied to the circuit in which respective faults will show up. For digital circuits the set of faults is often the set of “stuck at” faults for circuit nodes, wherein the logic signal remains at the same level irrespective of input signals. Test input signals are selected that should normally affect the logic level at the node and test output signals are selected that should normally depend on the logic level of the node.
Planning of analog circuit testing likewise involves selecting a set of faults and test input and output signals that show up these faults. However, in analog circuits the test output signals of different fault free circuits will be spread due to natural parameter spread. Similarly the test output signals of different circuits with the same fault will be spread. Accordingly, tests must be selected where the output signal spread of fault free and faulty circuits have little or no overlap.
A method of evaluating test signals is disclosed in an article by Fang Liu et al titled “Fast Hierarchical Process Variability Analysis and Parametric test Development for Analog/RF Circuits”, in the Proceedings of the 2005 International conference on computer design (ICCD'05). Fang Liu sets each component parameter values to a series abnormal values and evaluates whether a functional test output signal is sufficiently affected by this that the spread in this output signal of circuits with this fault does not, or only insignificantly, overlap with the spread in this output signal of normal circuits. Fang Liu uses this to compute the effect on functional signals of all parameters of all transistors.
Fang Liu uses a linearized model to compute the effect of the faults and spread of parameters. Thus, even though a significant amount of computation is required, test signals can be evaluated for fairly complex circuits. From this a selection of test input and output signals can be made in which any selected fault in any component can be detected.
However, for analog circuits this approach does not properly predict detectability of faulty circuits. One reason for this is that deviations of component parameter values (both normal and abnormal deviations) may be correlated. If no account of this is taken the computed output signal spread for circuits with components with normal and abnormal parameter values does not correspond to reality, with the effect that fault coverage is not predicted correctly. On the other hand, taking account of all possible correlations may considerably increase the required amount of computation.